The present invention relates to an analog-to-digital converter and in particular, to an analog-to-digital converter suitable for high speed operation.
The typical analog-to-digital converter suitable for high speed operation has heretofore been the flash type analog-to-digital converter. In this type of analog-to-digital converter, an analog input signal is supplied in parallel to each of 2n comparators of an n-bit analog-to-digital converter for simultaneously performing a comparison operation. If the A/D converter is of a 6 bit type, an analog input signal is supplied in parallel to, for example, the inputs of 2.sup.6, i.e. 64, comparators. Therefore, as the number of bits increases, the electrostatic capacitance established in the input circuits increases remarkably, causing the conversion speed to be lowered remarkably.
On the other hand, the total length of a conductor which connects the input circuits with each other causes a remarkably long delay in transmission as the number of bits increases. This gives an adverse influence to the higher speed operation of the A/D converter. Even if comparators of the A/D converter which are spaced at an average length of 100 microns are finely formed in an integrated circuit, the conductors of the 6 and 8 bit A/D converters are 6400 and 25600 microns in total length, respectively.
If it is assumed that the stray capacitance and the line inductance per one micron are 1 femtofarad and 0.1 nano henry respectively, the total static capacitance of the input circuit would be 6.4 and 25.6 pico farads and the line inductance thereof would be 640 nano henry and 2560 micro henry for 6 and 8 bit A/D converters, respectively. If the input circuit has such a high reactance, the cut-off frequency of the input circuit is as low as 100 MHz and 20 MHz. This makes it very difficult to provide an A/D converter which can be operated at a high speed.
The structure of such a conventional A/D converter will now be described. Referring now to FIG. 1, there is shown as a part of the input circuit of an A/D converter. A reference mark VIN denotes a signal input line through which a signal which will be analog-to-digital converted is transmitted; VRT denotes a comparing higher reference voltage input line; VRB denotes a comparing lower reference voltage input line; 1 denotes comparators A0, A1, A2, . . . A254 and A255; 2 denotes a group of comparing reference voltage dividing resistors R; 3 denotes an encoder for encoding an output signal from each comparator into a digital signal; CLOCK IN denotes a reference clock signal input line for clocking the A/D conversion; 4 a driver circuit for supplying the clock signal to the encoder 3 and an output circuit 5; 5 the output circuit for supplying the digital output to an external circuit; OUTPUT denotes data outputs; and CST denotes an input static capacitance of each comparing circuit 1.
Referring now to FIG. 2, there is shown an example of a semiconductor mask layout of the above mentioned 8 bit flash type A/D converter. The signal input line VIN is branched into four lines for reducing the attenuation of the input signal due to filtering caused by the stray capacitance and the line inductance. The total length of each of the four branches of the signal input line VIN is shortened by arranging the comparator group 1 in four columns.
Referring now to FIG. 3, there is illustrated the signal input line VIN of the semiconductor mask layout. The signal input line VIN is branched into four branched input signal lines IN1, IN2, IN3 and IN4 which leads to an input terminal of each comparator 1. FIG. 4 shows a circuit diagram of this semiconductor mask layout.
Since the comparators which are connected to each of the branched input signal lines IN1, IN2, IN3 and IN4 are 64 in number in the above mentioned conventional A/D converter as shown in FIG. 4, the total stray capacitance of the entire signal input line VIN is not decreased although the total length of the input signal lines is a little over 6 mm. Accordingly, although the lowering of the frequency characteristics at end points of the branched input signal lines IN1, IN2, IN3 and IN4 is mitigated, loading of capacitance imposed upon the external circuit which supplies a high frequency signal to the signal input line VIN remains as very high as ever.
For example, an electrostatic capacitance of 25.6 pico farads serves as an a reactance of 62.2 ohms for a sinusoidal signal having an amplitude of one volt and a frequency of 100 MHz and consumes a high frequency current of at most 16 mA. Since the influence of the electrostatic capacitance becomes remarkable as the frequency increases, a simple calculation shows that the reactance is 6.3 ohms and the consumed high frequency current is 160 mA for the 1000 MHz sinusoidal signal.